| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u12 |
4 |
2 |
0 |
2 |
3 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u11|altshift_taps_component|auto_generated|cntr1|cmpr5 |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u11|altshift_taps_component|auto_generated|cntr1 |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u11|altshift_taps_component|auto_generated|altsyncram2 |
39 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u11|altshift_taps_component|auto_generated |
18 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u11 |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u10|altshift_taps_component|auto_generated|cntr1|cmpr5 |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u10|altshift_taps_component|auto_generated|cntr1 |
2 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u10|altshift_taps_component|auto_generated|altsyncram2 |
39 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u10|altshift_taps_component|auto_generated |
18 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u10 |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pwm2 |
24 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pwm1 |
24 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| mc |
12 |
0 |
0 |
0 |
52 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Cd1 |
52 |
10 |
1 |
10 |
40 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u9 |
32 |
1 |
0 |
1 |
58 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult3|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult3 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult2|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult2 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult1|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult1 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u2|ALTMULT_ADD_component|auto_generated |
77 |
0 |
0 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u2 |
77 |
51 |
0 |
51 |
27 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult3|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult3 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult2|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult2 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult1|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult1 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u1|ALTMULT_ADD_component|auto_generated |
77 |
0 |
0 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u1 |
77 |
51 |
0 |
51 |
27 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult3|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult3 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult2|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult2 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult1|pre_result |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult1 |
37 |
9 |
0 |
9 |
25 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u8|u0|ALTMULT_ADD_component|auto_generated |
77 |
0 |
0 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u0 |
77 |
51 |
0 |
51 |
27 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u8 |
27 |
0 |
0 |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7 |
28 |
0 |
9 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|data_path1 |
20 |
2 |
0 |
2 |
18 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u6|command1 |
35 |
0 |
2 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|control1 |
30 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|sdram_pll1 |
1 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6 |
192 |
167 |
0 |
167 |
57 |
167 |
167 |
167 |
16 |
0 |
0 |
0 |
0 |
| u5|lpm_divide_component|auto_generated|divider|divider|add_sub_1 |
4 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|lpm_divide_component|auto_generated|divider|divider|add_sub_0 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|lpm_divide_component|auto_generated|divider|divider |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|lpm_divide_component|auto_generated|divider |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|lpm_divide_component|auto_generated |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5 |
16 |
4 |
0 |
4 |
14 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u4 |
12 |
0 |
0 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u3 |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u1|u0 |
27 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| u1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| u0|u7 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|u6 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|u5 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|u4 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|u3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|u2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|u1 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|u0 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0 |
32 |
14 |
0 |
14 |
56 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |